//------------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited.
//
//            (C) COPYRIGHT 2008-2012 ARM Limited.
//                ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited.
//------------------------------------------------------------------------------
// Version and Release Control Information:
//
// File Revision       : 127275
// File Date           :  2012-03-19 15:37:15 +0000 (Mon, 19 Mar 2012)
// Release Information : PL401-r0p1-00eac0
//------------------------------------------------------------------------------
// Purpose : HDL defines file for AMBA interface block
//           AUTOMATICALLY GENERATED, ONLY MODIFY MARKED SECTIONS
//------------------------------------------------------------------------------

// Reg Slice configuration defines
`undef RS_REGD
`undef RS_FWD_REG
`undef RS_REV_REG
`undef RS_STATIC_BYPASS

// slave_if_data_width  64
// slave_if_protocol    axi4

// master_if_data_width 32
// master_if_protocol   axi4
// AMBA downsizer defines
`undef AWFIFO_BYPASS
`undef AWFIFO_SIZE
`undef AWFIFO_ADDR
`undef AWFIFO_MASK
`undef AWFIFO_WRAP_FITS


`undef ARDATA_SIZE
`undef ARDATA_BYPASS
`undef ARDATA_ADDR
`undef ARDATA_MASK
`undef ARDATA_END
`undef ARDATA_ID
`undef ARDATA_TWO
`undef ARDATA_WRAP_FITS


//------------------------------------------------------------------------------
// nic400_ib_vgalcd_mst_axi4_ib_aw_fifo Pointer Encoding
//------------------------------------------------------------------------------
  
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AW_FIFO_0_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AW_FIFO_0_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AW_FIFO_1_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AW_FIFO_1_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AW_FIFO_x_x



//------------------------------------------------------------------------------
// nic400_ib_vgalcd_mst_axi4_ib_ar_fifo Pointer Encoding
//------------------------------------------------------------------------------
  
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AR_FIFO_0_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AR_FIFO_0_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AR_FIFO_1_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AR_FIFO_1_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_AR_FIFO_x_x



//------------------------------------------------------------------------------
// nic400_ib_vgalcd_mst_axi4_ib_r_fifo Pointer Encoding
//------------------------------------------------------------------------------
  
`undef NIC400_IB_VGALCD_MST_AXI4_IB_R_FIFO_0_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_R_FIFO_0_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_R_FIFO_1_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_R_FIFO_1_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_R_FIFO_x_x



//------------------------------------------------------------------------------
// nic400_ib_vgalcd_mst_axi4_ib_w_fifo Pointer Encoding
//------------------------------------------------------------------------------
  
`undef NIC400_IB_VGALCD_MST_AXI4_IB_W_FIFO_0_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_W_FIFO_0_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_W_FIFO_1_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_W_FIFO_1_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_W_FIFO_x_x



//------------------------------------------------------------------------------
// nic400_ib_vgalcd_mst_axi4_ib_b_fifo Pointer Encoding
//------------------------------------------------------------------------------
  
`undef NIC400_IB_VGALCD_MST_AXI4_IB_B_FIFO_0_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_B_FIFO_0_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_B_FIFO_1_0
`undef NIC400_IB_VGALCD_MST_AXI4_IB_B_FIFO_1_1
`undef NIC400_IB_VGALCD_MST_AXI4_IB_B_FIFO_x_x




//------------------------------------------------------------------------------
// End of File
//------------------------------------------------------------------------------

